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In our example, we had to list all the object files twice in the rule for edit repeated here :. Such duplication is error-prone; if a new object file is added to the system, we might add it to one list and forget the other. We can eliminate the risk and simplify the makefile by using a variable. Variables allow a text string to be defined once and substituted in multiple places later see How to Use Variables. We would define such a variable objects with a line like this in the makefile:.

We can therefore omit the recipes from the rules for the object files. See Using Implicit Rules. Here is the entire example, with both of these changes, and a variable objects as suggested above:. This is how we would write the makefile in actual practice. See Phony Targets , and Errors in Recipes. Because implicit rules are so convenient, they are important. You will see them used frequently. When the objects of a makefile are created only by implicit rules, an alternative style of makefile is possible.

In this style of makefile, you group entries by their prerequisites instead of by their targets. Here is what one looks like:. Here defs. Whether this is better is a matter of taste: it is more compact, but some people dislike it because they find it clearer to put all the information about each target in one place. Compiling a program is not the only thing you might want to write rules for. In practice, we might want to write the rule in a somewhat more complicated manner to handle unanticipated situations.

We would do this:. This prevents make from getting confused by an actual file called clean and causes it to continue in spite of errors from rm. A rule such as this should not be placed at the beginning of the makefile, because we do not want it to run by default!

Thus, in the example makefile, we want the rule for edit , which recompiles the editor, to remain the default goal. The information that tells make how to recompile a system comes from reading a data base called the makefile. Makefiles contain five kinds of things: explicit rules , implicit rules , variable definitions , directives , and comments. Rules, variables, and directives are described at length in later chapters.

You cannot use comments within variable references or function calls: any instance of will be treated literally rather than as the start of a comment inside a variable reference or function call. Comments within a recipe are passed to the shell, just as with any other recipe text. The shell decides how to interpret it: whether or not this is a comment is up to the shell. Within a define directive, comments are not ignored during the definition of the variable, but rather kept intact in the value of the variable.

When the variable is expanded they will either be treated as make comments or as recipe text, depending on the context in which the variable is evaluated. GNU make has no limit on the length of a statement line, up to the amount of memory in your computer.

However, it is difficult to read lines which are too long to display without wrapping or scrolling. If the. Then make will perform variable expansion.

By default, when make looks for the makefile, it tries the following names, in order: GNUmakefile , makefile and Makefile. Normally you should call your makefile either makefile or Makefile. We recommend Makefile because it appears prominently near the beginning of a directory listing, right near other important files such as README.

The first name checked, GNUmakefile , is not recommended for most makefiles. You should use this name if you have a makefile that is specific to GNU make , and will not be understood by other versions of make. Other make programs look for makefile and Makefile , but not GNUmakefile.

If make finds none of these names, it does not use any makefile. Then you must specify a goal with a command argument, and make will attempt to figure out how to remake it using only its built-in implicit rules.

All the makefiles are effectively concatenated in the order specified. The include directive tells make to suspend reading the current makefile and read one or more other makefiles before continuing. The directive is a line in the makefile that looks like this:.

If filenames is empty, nothing is included and no error is printed. Extra spaces are allowed and ignored at the beginning of the line, but the first character must not be a tab or the value of.

Whitespace is required between include and the file names, and between file names; extra whitespace is ignored there and at the end of the directive. If the file names contain any variable or function references, they are expanded. See How to Use Variables. For example, if you have three. When make processes an include directive, it suspends reading of the containing makefile and reads from each listed file in turn.

When that is finished, make resumes reading the makefile in which the directive appears. One occasion for using include directives is when several programs, handled by individual makefiles in various directories, need to use a common set of variable definitions see Setting Variables or pattern rules see Defining and Redefining Pattern Rules.

Another such occasion is when you want to generate prerequisites from source files automatically; the prerequisites can be put in a file that is included by the main makefile. This practice is generally cleaner than that of somehow appending the prerequisites to the end of the main makefile as has been traditionally done with other versions of make.

See Automatic Prerequisites. If the specified name does not start with a slash, and the file is not found in the current directory, several other directories are searched. If an included makefile cannot be found in any of these directories, a warning message is generated, but it is not an immediately fatal error; processing of the makefile containing the include continues.

See How Makefiles Are Remade. Only after it has tried to find a way to remake a makefile and failed, will make diagnose the missing makefile as a fatal error. If you want make to simply ignore a makefile which does not exist or cannot be remade, with no error message, use the -include directive instead of include , like this:.

This acts like include in every way except that there is no error not even a warning if any of the filenames or any prerequisites of any of the filenames do not exist or cannot be remade. For compatibility with some other make implementations, sinclude is another name for -include.

If the environment variable MAKEFILES is defined, make considers its value as a list of names separated by whitespace of additional makefiles to be read before the others. This works much like the include directive: various directories are searched for those files see Including Other Makefiles.

In addition, the default goal is never taken from one of these makefiles or any makefile included by them and it is not an error if the files listed in MAKEFILES are not found.

It usually is not desirable to set the environment variable before a top-level invocation of make , because it is usually better not to mess with a makefile from outside. However, if you are running make without a specific makefile, a makefile in MAKEFILES can do useful things to help the built-in implicit rules work better, such as defining search paths see Directory Search.

This is a very bad idea, because such makefiles will fail to work if run by anyone else. It is much better to write explicit include directives in the makefiles. See Including Other Makefiles. If a makefile can be remade from other files, you probably want make to get an up-to-date version of the makefile to read in. To this end, after reading in all makefiles make will consider each as a goal target and attempt to update it. If a makefile has a rule which says how to update it found either in that very makefile or in another one or if an implicit rule applies to it see Using Implicit Rules , it will be updated if necessary.

After all makefiles have been checked, if any have actually been changed, make starts with a clean slate and reads all the makefiles over again. It will also attempt to update each of them over again, but normally this will not change them again, since they are already up to date.

If you know that one or more of your makefiles cannot be remade and you want to keep make from performing an implicit rule search on them, perhaps for efficiency reasons, you can use any normal method of preventing implicit rule look-up to do so. For example, you can write an explicit rule with the makefile as the target, and an empty recipe see Using Empty Recipes. If the makefiles specify a double-colon rule to remake a file with a recipe but no prerequisites, that file will always be remade see Double-Colon.

In the case of makefiles, a makefile that has a double-colon rule with a recipe but no prerequisites will be remade every time make is run, and then again after make starts over and reads the makefiles in again. This would cause an infinite loop: make would constantly remake the makefile, and never do anything else. So, to avoid this, make will not attempt to remake makefiles which are specified as targets of a double-colon rule with a recipe but no prerequisites.

However, if a default makefile does not exist but can be created by running make rules, you probably want the rules to be run so that the makefile can be used. Therefore, if none of the default makefiles exists, make will try to make each of them in the same order in which they are searched for see What Name to Give Your Makefile until it succeeds in making one, or it runs out of names to try.

Note that it is not an error if make cannot find or make any makefile; a makefile is not always necessary. The recipe printed for foo will be the one specified in the updated contents of mfile. However, on occasion you might actually wish to prevent updating of even the makefiles.

You can do this by specifying the makefiles as goals in the command line as well as specifying them as makefiles. The recipe for foo will be the one specified by the existing contents of mfile. Sometimes it is useful to have a makefile that is mostly just like another makefile. However, it is invalid for two makefiles to give different recipes for the same target. But there is another way. In the containing makefile the one that wants to include the other , you can use a match-anything pattern rule to say that to remake any target that cannot be made from the information in the containing makefile, make should look in another makefile.

See Pattern Rules , for more information on pattern rules. If Makefile provides a rule for updating bar , make will apply the rule. And likewise for any other target that GNUmakefile does not say how to make.

The rule specifies a prerequisite force , to guarantee that the recipe will be run even if the target file already exists. We give the force target an empty recipe to prevent make from searching for an implicit rule to build it—otherwise it would apply the same match-anything rule to force itself and create a prerequisite loop!

GNU make does its work in two distinct phases. During the first phase it reads all the makefiles, included makefiles, etc. During the second phase, make uses this internalized data to determine which targets need to be updated and run the recipes necessary to update them.

Below is a summary of the different constructs that can be found in a makefile, and the phase in which expansion happens for each part of the construct.

We say that expansion is immediate if it happens during the first phase: make will expand that part of the construct as the makefile is parsed. We say that expansion is deferred if it is not immediate. Expansion of a deferred construct part is delayed until the expansion is used: either when it is referenced in an immediate context, or when it is needed during the second phase.

You may not be familiar with some of these constructs yet. You can reference this section as you become familiar with them, in later chapters. The result is stored in the variable named on the left, and that variable becomes a simple variable and will thus be re-evaluated on each reference. Conditional directives are parsed immediately. This means, for example, that automatic variables cannot be used in conditional directives, as automatic variables are not set until the recipe for that rule is invoked.

If you need to use automatic variables in a conditional directive you must move the condition into the recipe and use shell conditional syntax instead. That is, the target and prerequisite sections are expanded immediately, and the recipe used to build the target is always deferred. This is true for explicit rules, pattern rules, suffix rules, static pattern rules, and simple prerequisite definitions.

GNU make parses makefiles line-by-line. Parsing proceeds using the following steps:. An important consequence of this is that a macro can expand to an entire rule, if it is one line long. This will work:. However, this will not work because make does not re-split lines after it has expanded them:. Newlines still present in a line after expansion is complete are ignored as normal whitespace. In order to properly expand a multi-line macro you must use the eval function: this causes the make parser to be run on the results of the expanded macro see Eval Function.

Previously we learned that GNU make works in two distinct phases: a read-in phase and a target-update phase see How make Reads a Makefile. GNU make also has the ability to enable a second expansion of the prerequisites only for some or all targets defined in the makefile. In order for this second expansion to occur, the special target. If that special target is defined then in between the two phases mentioned above, right at the end of the read-in phase, all the prerequisites of the targets defined after the special target are expanded a second time.

In most circumstances this secondary expansion will have no effect, since all variable and function references will have been expanded during the initial parsing of the makefiles. For example, consider this makefile:. Now during the secondary expansion the first word is expanded again but since it contains no variable or function references it remains the value onefile , while the second word is now a normal reference to the variable TWOVAR , which is expanded to the value twofile.

The final result is that there are two prerequisites, onefile and twofile. Obviously, this is not a very interesting case since the same result could more easily have been achieved simply by having both variables appear, unescaped, in the prerequisites list.

One difference becomes apparent if the variables are reset; consider this example:. Here the prerequisite of onefile will be expanded immediately, and resolve to the value top , while the prerequisite of twofile will not be full expanded until the secondary expansion and yield a value of bottom. This is marginally more exciting, but the true power of this feature only becomes apparent when you discover that secondary expansions always take place within the scope of the automatic variables for that target.

Also, secondary expansion occurs for both explicit and implicit pattern rules. Knowing this, the possible uses for this feature increase dramatically.

For example:. This version allows users to specify source files rather than object files, but gives the same resulting prerequisites list as the previous example.

The subtleties of using the different automatic variables are described below. The following example will help illustrate these behaviors:.

In the second, they will have values foo. In the third they will have values foo. Rules undergo secondary expansion in makefile order, except that the rule with the recipe is always evaluated last. As make searches for an implicit rule, it substitutes the stem and then performs secondary expansion for every rule with a matching target pattern.

The value of the automatic variables is derived in the same fashion as for static pattern rules. As an example:. Note that the directory prefix D , as described in Implicit Rule Search Algorithm , is appended after expansion to all the patterns in the prerequisites list.

It lists the other files that are the prerequisites of the target, and the recipe to use to create or update the target. The order of rules is not significant, except for determining the default goal : the target for make to consider, if you do not otherwise specify one.

The default goal is the target of the first rule in the first makefile. If the first rule has multiple targets, only the first target is taken as the default. See Defining and Redefining Pattern Rules. See Arguments to Specify the Goals. Its target is foo. The recipe starts with a tab to identify it as a recipe. The targets are file names, separated by spaces. Wildcard characters may be used see Using Wildcard Characters in File Names and a name of the form a m represents member m in archive file a see Archive Members as Targets.

Usually there is only one target per rule, but occasionally there is a reason to have more see Multiple Targets in a Rule. The recipe lines start with a tab character or the first character in the value of the. The first recipe line may appear on the line after the prerequisites, with a tab character, or may appear on the same line, with a semicolon. Either way, the effect is the same. There are other differences in the syntax of recipes.

See Writing Recipes in Rules. You may split a long line by inserting a backslash followed by a newline, but this is not required, as make places no limit on the length of a line in a makefile. A rule tells make two things: when the targets are out of date, and how to update them when necessary. The criterion for being out of date is specified in terms of the prerequisites , which consist of file names separated by spaces.

Wildcards and archive members see Archives are allowed here too. A target is out of date if it does not exist or if it is older than any of the prerequisites by comparison of last-modification times. The idea is that the contents of the target file are computed based on information in the prerequisites, so if any of the prerequisites changes, the contents of the existing target file are no longer necessarily valid. How to update is specified by a recipe. There are actually two different types of prerequisites understood by GNU make : normal prerequisites such as described in the previous section, and order-only prerequisites.

A normal prerequisite makes two statements: first, it imposes an order in which recipes will be invoked: the recipes for all prerequisites of a target will be completed before the recipe for the target is run.

Second, it imposes a dependency relationship: if any prerequisite is newer than the target, then the target is considered out-of-date and must be rebuilt. Occasionally, however, you have a situation where you want to impose a specific ordering on the rules to be invoked without forcing the target to be updated if one of those rules is executed. In that case, you want to define order-only prerequisites.

Order-only prerequisites can be specified by placing a pipe symbol in the prerequisites list: any prerequisites to the left of the pipe symbol are normal; any prerequisites to the right are order-only:. The normal prerequisites section may of course be empty. Also, you may still declare multiple lines of prerequisites for the same target: they are appended appropriately normal prerequisites are appended to the list of normal prerequisites; order-only prerequisites are appended to the list of order-only prerequisites.

Note that if you declare the same file to be both a normal and an order-only prerequisite, the normal prerequisite takes precedence since they have a strict superset of the behavior of an order-only prerequisite. Consider an example where your targets are to be placed in a separate directory, and that directory might not exist before make is run.

One way to manage this is with order-only prerequisites: make the directory an order-only prerequisite on all the targets:. A single file name can specify many files using wildcard characters. If alone, or followed by a slash, it represents your home directory. Wildcard expansion is performed by make automatically in targets and in prerequisites. In recipes, the shell is responsible for wildcard expansion.

In other contexts, wildcard expansion happens only if you request it explicitly with the wildcard function. The special significance of a wildcard character can be turned off by preceding it with a backslash. Wildcards can be used in the recipe of a rule, where they are expanded by the shell. For example, here is a rule to delete all the object files:. Wildcards are also useful in the prerequisites of a rule. However, if you use the value of objects in a target or prerequisite, wildcard expansion will take place there.

If you use the value of objects in a recipe, the shell may perform wildcard expansion when the recipe runs. To set objects to the expansion, instead use:. Now here is an example of a naive way of using wildcard expansion, that does not do what you would intend. Suppose you would like to say that the executable file foo is made from all the object files in the directory, and you write this:. This is not what you want!

Actually it is possible to obtain the desired result with wildcard expansion, but you need more sophisticated techniques, including the wildcard function and string substitution. See The Function wildcard. When make runs on these systems, it supports backslashes as well as the Unix-style forward slashes in pathnames. However, this support does not include the wildcard expansion, where backslash is a quote character.

Therefore, you must use Unix-style slashes in these cases. Wildcard expansion happens automatically in rules. But wildcard expansion does not normally take place when a variable is set, or inside the arguments of a function. If you want to do wildcard expansion in such places, you need to use the wildcard function, like this:. This string, used anywhere in a makefile, is replaced by a space-separated list of names of existing files that match one of the given file name patterns.

If no existing file name matches a pattern, then that pattern is omitted from the output of the wildcard function. Note that this is different from how unmatched wildcards behave in rules, where they are used verbatim rather than ignored see Wildcard Pitfall. One use of the wildcard function is to get a list of all the C source files in a directory, like this:.

Here we have used another function, patsubst. See Functions for String Substitution and Analysis. Thus, a makefile to compile all C source files in the directory and then link them together could be written as follows:. This takes advantage of the implicit rule for compiling C programs, so there is no need to write explicit rules for compiling the files. For large systems, it is often desirable to put sources in a separate directory from the binaries. The directory search features of make facilitate this by searching several directories automatically to find a prerequisite.

When you redistribute the files among directories, you do not need to change the individual rules, just the search paths. Most often, the directories are expected to contain prerequisite files that are not in the current directory; however, make uses VPATH as a search list for both prerequisites and targets of rules.

Thus, if a file that is listed as a target or prerequisite does not exist in the current directory, make searches the directories listed in VPATH for a file with that name. If a file is found in one of them, that file may become the prerequisite see below.

Rules may then specify the names of files in the prerequisite list as if they all existed in the current directory. See Writing Recipes with Directory Search. The order in which directories are listed is the order followed by make in its search.

Similar to the VPATH variable, but more selective, is the vpath directive note lower case , which allows you to specify a search path for a particular class of file names: those that match a particular pattern. Thus you can supply certain search directories for one class of file names and other directories or none for other file names. When a prerequisite fails to exist in the current directory, if the pattern in a vpath directive matches the name of the prerequisite file, then the directories in that directive are searched just like and before the directories in the VPATH variable.

When a prerequisite is found through directory search, regardless of type general or selective , the pathname located may not be the one that make actually provides you in the prerequisite list. Sometimes the path discovered through directory search is thrown away.

The algorithm make uses to decide whether to keep or abandon a path found via directory search is as follows:. Other versions of make use a simpler algorithm: if the file does not exist, and it is found via directory search, then that pathname is always used whether or not the target needs to be built.

Thus, if the target is rebuilt it is created at the pathname discovered during directory search. If, in fact, this is the behavior you want for some or all of your directories, you can use the GPATH variable to indicate this to make. If an out-of-date target is found by directory search in a directory that also appears in GPATH , then that pathname is not thrown away. The target is rebuilt using the expanded path.

When a prerequisite is found in another directory through directory search, this cannot change the recipe of the rule; they will execute as written. Therefore, you must write the recipe with care so that it will look for the prerequisite in the directory where make finds it. Often the prerequisites include header files as well, which you do not want to mention in the recipe.

For example, when a file foo. If such a file is lacking in the current directory, the appropriate directories are searched for it. If foo. The recipes of implicit rules normally use automatic variables as a matter of necessity; consequently they will use the file names found by directory search with no extra effort. Directory search applies in a special way to libraries used with the linker.

You can tell something strange is going on here because the prerequisite is normally the name of a file, and the file name of a library generally looks like lib name. Although the default set of files to be searched for is lib name. Each word in the value of this variable is a pattern string. The default value for. A phony target is one that is not really the name of a file; rather it is just a name for a recipe to be executed when you make an explicit request.

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